Nano Archive

IDD scan test method for fault localization technique on CMOS VLSI failure analysis

Abdullah, F and Nayan, N and Jamil, M.M.A and Kamsin, N. (2010) IDD scan test method for fault localization technique on CMOS VLSI failure analysis. 2010 IEEE International Conference on Semiconductor Electronics (ICSE) .

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Abstract

One of the fashionable stress test that has been practiced in CMOS VLSI recently is known as IDDQ scan test. It has competency to be exercised as a part of failure analysis method in localization latent defect with nano scale geometry, i.e. gate oxide hole. An extension study in this field delivers proficiency on logic circuit diagnostic. Form the results obtained during the experiment, it shows that the IDD scan test can be applied effectively in triggering significant emission spot during anomalous logic transition.

Item Type:Article
Additional Information:2010 IEEE International Conference on Semiconductor Electronics (ICSE) Melaka, Malaysia, 28-30 June 2010
Uncontrolled Keywords:IDD scan test method; fault localization; CMOS VLSI failure analysis; localization latent defect; nano scale geometry; gate oxide hole; logic circuit diagnostic
Subjects:Material Science > Nanostructured materials
ID Code:9747
Deposited By:CSMNT
Deposited On:26 Oct 2010 14:20
Last Modified:26 Oct 2010 14:20

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