Nano Archive

Run-time data-dependent defect tolerance for hybrid CMOS/nanodevice digital memories

Sun, Fei and Feng, Lu and Zhang, Tong (2008) Run-time data-dependent defect tolerance for hybrid CMOS/nanodevice digital memories. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 7 (2). pp. 217-222.

Full text is not hosted in this archive but may be available via the Official URL, or by requesting a copy from the corresponding author.

Official URL: http://ieeexplore.ieee.org/Xplore/login.jsp?url=ht...

Abstract

This paper presents a data-dependent defect tolerance design approach to improve the storage capacity of defect-prone hybrid CMOS/nanodevice digital memories. The basic idea is to reduce the memory redundancy overhead by exploiting the run-time matching between the data and memory defects. A conditional bit-flipping technique is used to enable the practical realization of this design approach in presence of the conflict between the dynamic nature of run-time data-defect matching and static nature of memory system design. Computer simulations show that the proposed method can achieve much higher storage capacity compared with conventional data-independent defect tolerance at small memory operation overhead.

Item Type:Article
Uncontrolled Keywords:CMOS; defect tolerance; digital memory; error control codes; nano device; storage capacity
Subjects:Physical Science > Nanoelectronics
Engineering > Nanotechnology applications in ICT
ID Code:6132
Deposited By:IoN
Deposited On:05 Aug 2009 10:39
Last Modified:05 Aug 2009 10:39

Repository Staff Only: item control page