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Characterization of sub-100 nm CMOS process using screening experiment technique

Srinivasaiah, H.C. and Bhat, Navakanta (2005) Characterization of sub-100 nm CMOS process using screening experiment technique. Solid-State Electronics, 49 (3). pp. 431-436.

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The relative sensitivity of the CMOS device parameters on various process steps are evaluated through a systematic study. A large set of 21 process parameters that could affect the device behavior have been investigated through Plackett–Burman screening design of experiment for 100 nm CMOS disposable spacer process technique. First-order regression models obtained from the experimental data in terms of these 21 process parameters, for threshold voltage Vtsat, subthreshold slope SSsat, on-state current Idsatdrive, and leakage current Idsatleak in the saturation region, are used to determine the statistical significance of each process parameters in terms of their rank. The ranking order, indicating the statistical significance of the respective process parameters, differs between NMOS and PMOS devices. Further, a sub-set of top 10 significant process parameters are picked for NMOS device, to perform Monte-Carlo process/device simulations to estimate the statistics of the device parameters. Monte-Carlo process/device simulations were also performed in terms of all the 21 process parameters, and the statistics are again evaluated. The statistics that are computed with 10 and 21 parameters are indeed close, implying the variability arising from the remaining 11 relatively insignificant parameters is negligible. This choice of the subset of 10 significant process parameters simplifies the Design of Experiment, for second-order response-surface-modeling for a detailed study of the CMOS process.

Item Type:Article
Subjects:Physical Science > Nanoelectronics
Divisions:Faculty of Engineering, Science and Mathematics > School of Electronics and Computer Science
ID Code:4068
Deposited By:JNCASR
Deposited On:03 Apr 2009 06:35
Last Modified:07 May 2009 13:06

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