Nano Archive

Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties

Lee, Jang-Sik and Cho, Jinhan and Lee, Chiyoung and Kim, Inpyo and Park, Jeongju and Kim, Yong-Mu and Shin, Hyunjung and Lee, Jaegab and Caruso, Frank (2007) Layer-by-layer assembled charge-trap memory devices with adjustable electronic properties. NATURE NANOTECHNOLOGY, 2 (12). pp. 790-795.

Full text is not hosted in this archive but may be available via the Official URL, or by requesting a copy from the corresponding author.

Official URL:


We describe a versatile approach for preparing flash memory devices composed of polyelectrolyte/gold nanoparticle multilayer films. Anionic gold nanoparticles were used as the charge storage elements, and poly(allylamine)/poly(styrenesulfonate) multilayers deposited onto hafnium oxide (HfO2)-coated silicon substrates formed the insulating layers. The top contact was formed by depositing HfO2 and platinum. In this study, we investigated the effect of increasing the number of polyelectrolyte and gold nanoparticle layers on memory performance, including the size of the memory window (the critical voltage difference between the `programmed' and `erased' states of the devices) and programming speed. We observed a maximum memory window of about 1.8 V, with a stored electron density of 4.2 x 10(12) cm(-2) in the gold nanoparticle layers, when the devices consist of three polyelectrolyte/gold nanoparticle layers. The reported approach offers new opportunities to prepare nanostructured polyelectrolyte/gold nanoparticle-based memory devices with tailored performance.

Item Type:Article
Subjects:Material Science > Nanofabrication processes and tools
Physical Science > Nanoelectronics
Engineering > Nanotechnology applications in ICT
ID Code:2674
Deposited By:Anuj Seth
Deposited On:09 Jan 2009 09:48
Last Modified:09 Jan 2009 17:05

Repository Staff Only: item control page