Nano Archive

Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array.

Ju.A., Diachenko Ju.G.Petruchin V.S. Stepchenkov (2006) Experience in Self-Timed Microcontroller Core Design on Basic Gate-Array. Journal of NANO and MICROSYSTEM TECHNIQUE, 5 (5). pp. 29-36.

Full text is not hosted in this archive but may be available via the Official URL, or by requesting a copy from the corresponding author.

Official URL:


The article considers state and design problems of strictly self-timed (SST) electronic circuits. SST-circuits are «naturally reliable» as they guarantee preservation of capacity for work of the device in the wide range of environment conditions comparable to the physical restrictions for integrated circuits. The SST-circuitry to the full meets the requirements, showed to element base for critical areas of applications.This article is devoted to development of effective means for designing and fabrication the SST-VLS1 on home Gate Array (GA) 5503 basis. The preliminary results of the development (after simulation and topological design on native industrial CAD for basic gate-array «Kovcheg 2.6») of synchronous and SST-variants of test silicon «Microcore» are presented. This silicon implements functions of 8-bit microcontroller PIC18CXX (widely used in manufactured in Russia devices) computational core.

Item Type:Article
ID Code:2028
Deposited By:Prof. Alexey Ivanov
Deposited On:19 Dec 2008 13:21
Last Modified:20 Mar 2009 08:58

Repository Staff Only: item control page