Nano Archive

Design of Logic Gate Characteristics /or Double Gate sub-25 nm SOI CMOS Transistors /or Lower Power Applications

Masalsky, N.V. (2010) Design of Logic Gate Characteristics /or Double Gate sub-25 nm SOI CMOS Transistors /or Lower Power Applications. Journal of NANO and MICROSYSTEM TECHNIQUE (5).

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Official URL: http:// www.microsystems.ru

Abstract

Criteria of a choice of technological parameters for sub-25 nm double gate transistors with structure silicon on isolator for low-power applications are considered. Characteristics of one-cascade logic gates on the chosen type of transistors with length of the channel 22 nm are numerically investigated at a supply voltage of less than 1 V. The opportunity for creation of low-power circuitry in 100 GHz a range is shown. Keywords: double gate SOI nanotransistor, logic gate, low power

Item Type:Article
Additional Information:Full text is in Russian
ID Code:10261
Deposited By:Prof. Alexey Ivanov
Deposited On:08 Dec 2010 23:40
Last Modified:09 Dec 2010 09:29

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