Gubarev, V.A. (2009) Algorithm Execution Time Simulation (Modeling) for Digital System Models (Devices) Based on SOC VLSI Circuits. Journal of NANO and MICROSYSTEM TECHNIQUE (11).
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Inclusion of TLMs (transaction-level models) in system requirements specification for COS VLSI circuit models development may significantly decrease development risk for real system programmers and reduce SOC VLSI circuits development time.The purpose of this paper is to describe methods of algorithm execution time simulation for SOC VLSI models, developed with SystemC modeling language in module-type development. Keywords: SOC VLSI circuit, system model, execution time simulation (modeling).
|Additional Information:||Full text is in Russian|
|Deposited By:||Prof. Alexey Ivanov|
|Deposited On:||08 Dec 2010 23:39|
|Last Modified:||09 Dec 2010 09:29|
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